Wykaz publikacji wybranego autora

Jakub Szyduczyński, dr inż.

adiunkt

Wydział Informatyki, Elektroniki i Telekomunikacji
WIEiT-ke, Instytut Elektroniki

  • 2023

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika, elektrotechnika i technologie kosmiczne

  • 2018

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika i elektrotechnika

[poprzednia klasyfikacja] obszar nauk technicznych / dziedzina nauk technicznych / elektronika

Identyfikatory Autora Informacje o Autorze w systemach zewnętrznych

ORCID: 0000-0001-8513-7687 orcid iD

ResearcherID: DYC-2267-2022

Scopus: 55980585400

PBN: 5e7092ae878c28a04739a9df

System Informacyjny AGH (SkOs)

1
  • A new successive time balancing time-to-digital conversion method
2
  • A successive approximation time-to-digital converter with single set of delay lines for time interval measurements
3
  • Analysis of conversion time in asynchronous successive charge redistribution ADC with varying rate of charge transfer
4
  • Analytical approach to multiple memoryless backoff contention analysis
5
  • Architecture of successive approximation time-to-digital converter with single set of delay lines
6
  • Behavioral modelling and optimization of a cyclic feedback-based successive approximation TDC with dynamic delay equalization
7
  • Behavioral modelling and optimization of a cyclic feedback-based successive approximation TDC with dynamic delay equalization
8
  • Dynamic equalization of logic delays in feedback-based successive approximation TDCs
9
  • Event-driven charge redistribution analog-to-digital converter with simultaneous sampling and conversion
10
  • Method for recognizing order of signals
11
  • Optimized design of successive approximation time-to-digital converter with single set of delay lines
12
  • Optimizing time-to-digital converter architecture for successive approximation time measurements
13
  • Recovery of signals encoded by Sample-and-Hold Asynchronous Sigma-Delta Modulation
14
  • Sample-and-hold asynchronous sigma-delta time encoding machine
15
  • Successive approximation time-to-digital converters
16
  • System for recognizing order of signals
17
  • Systematization and comparison of the binary successive approximation variants
18
19
  • Upper bounds on unsuccessful transmission rate in persistent and non-persistent CSMA protocols
20
  • Voltage-to-digital converter with event-driven charge redistribution