Wykaz publikacji wybranego autora

Paweł Leonard Gryboś, prof. dr hab. inż.

profesor zwyczajny

Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
WEAIiIB-kmie, Katedra Metrologii i Elektroniki

  • 2023

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika, elektrotechnika i technologie kosmiczne

  • 2018

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika i elektrotechnika

[poprzednia klasyfikacja] obszar nauk technicznych / dziedzina nauk technicznych / elektronika

Identyfikatory Autora Informacje o Autorze w systemach zewnętrznych

ORCID: 0000-0003-2446-9033 orcid iD

ResearcherID: T-4530-2017

Scopus: 12793514000

PBN: 5e70922b878c28a047391138

OPI Nauka Polska

System Informacyjny AGH (SkOs)

1
  • 64 channel neural recording amplifier with tunable bandwidth in 180 nm CMOS technology
2
  • A 10-bit 3MS/s low-power charge redistribution ADC in 180nm CMOS for neural application
3
  • A bidirectional 64-channel neurochip for recording and stimulation neural network activity
4
  • A first-level event selector for the CBM experiment at FAIR
5
  • A low noise, fast pixel readout IC working in single photon counting mode with energy window selection in 90 nm CMOS
6
  • Analysis of full charge reconstruction algorithms for X-ray pixelated detectors
7
  • Comparision of two different architectures of multichannel readout ASICs for neurobiological experiments
8
  • Development of a fast readout chip in deep submicron technology for pixel hybrid detectors
9
  • Evolution of a prototype silicon strip detector readout ASIC for the STS
10
  • Fast hybrid pixel detectors with continuous readout in deep submicron and 3D technologies
11
  • FPDR90 – a low noise, fast pixel readout chip in 90 nm CMOS technology
12
  • FSDR16 a low noise, fast silicon strip detector readout IC with a 5th order complex shaping amplifier in 180 nm CMOS
13
  • Integrated control unit for wireless recording of brain activity
14
  • Low noise 64-channel ASIC for AC and DC coupled strip detectors
15
  • Low noise and low power multichannel integrated circuit for recording neural spikes and LFP signals
16
  • Low noise and low power multichannel integrated circuit for recording neural spikes and LFP signals
17
  • Measurements of low noise 64 channel counting ASIC for Si and CdTe strip detectors
18
  • Prototype readout electronics and silicon strip detector study for the silison tracking system at compressed baryonic matter experiment
19
  • PXD18k – fast single photon counting chip with energy window for hybrid pixel detector
20
  • Readout electronics for pixel detectors in deep submicron and 3D technologies
21
  • Tests of FPDR90 IC for hybrid detector readout for high frame rate X-ray applications
22
  • The design of low power low noise high speed CMOS readout front-end electronics for silicon strip detectors
23
  • TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors
24
  • TOT02, a time-over-threshold based readout chip in 180 nm CMOS process for long silicon strip detectors
25
  • Tuning the low cut-off frequency in multichannel neural recording amplifiers by the on-chip correction DACs