Wykaz publikacji wybranego autora

Ireneusz Brzozowski, dr inż.

adiunkt

Wydział Informatyki, Elektroniki i Telekomunikacji
WIEiT-ke, Instytut Elektroniki

  • 2023

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika, elektrotechnika i technologie kosmiczne

  • 2018

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika i elektrotechnika

[poprzednia klasyfikacja] obszar nauk technicznych / dziedzina nauk technicznych / elektronika

Identyfikatory Autora Informacje o Autorze w systemach zewnętrznych

ORCID: 0000-0002-1593-4047 orcid iD

ResearcherID: B-7954-2019

Scopus: 55946203800

PBN: 5e70922b878c28a0473910eb

OPI Nauka Polska

System Informacyjny AGH (SkOs)

1
  • An analysis of full adder cells for low-power data oriented adders design
2
  • An analysis of parallel prefix adders regarding the design of low-power data oriented adders
3
  • ASIC implementation of high efficiency 8-bit “OctaLynx” RISC microprocessor
4
  • ASICs design – education and research
5
  • Assessment and modelling of quasi-short power dissipation in CMOS gates
6
  • Breath sensor based on conductive foam
7
  • Calculation methods of new circuit activity measure for low power modeling
8
  • Comparative analysis of power consumption of parallel prefix adders
9
  • Design and analysis of multi-level $n-to-2^{n}$ decoders in CMOS technology
10
  • Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm
11
  • Electro-thermal analysis of integrated circuits using coupling of SPICE and COMSOL
12
  • Energy consumption minimisation with new synthesis method
13
  • Energy scavenging from waste heat and electromagnetic induction
14
  • Estimation and harvesting of human heat power for wearable electronic devices
15
  • Extraction of temperature dependent parameters for an electrothermal model of thermoelectric energy harvester
16
  • IDD current monitoring cell for VLSI circuits – design and testing
17
  • Input voltage impact on quasi-short power dissipation of CMOS gates
18
  • Low-power logic design based on {\em gate driving way} considering interconnections capacitances
19
  • Matrix of Thermal Characters for the blind
20
  • Minimisation of power consumption in digital integrated circuits by reduction of switching activity
21
  • Modelling of dynamic power dissipation for static CMOS gates and logic networks
22
  • Narzędzia do symulacji termicznej układów ASIC
23
  • Neuromorphic computing architecture based on serially connected magnetic tunnel junctions
24
  • New concept of low power digital circuits design
25
  • New idea of objective assessment of energy consumed by real VLSI gates